? semiconductor components industries, llc, 2015 march, 2015 ? rev. 8 1 publication order number: mc74ac257/d mc74ac257, mc74act257 quad 2-input multiplexer with 3-state outputs the mc74ac257/74act257 is a quad 2?input multiplexer with 3?state outputs. four bits of data from two sources can be selected using a common data select input. the four outputs present the selected data in true (noninverted) form. the outputs may be switched to a high impedance state by placing a logic high on the common output enable (oe ) input, allowing the outputs to interface directly with bus?oriented systems. ? multiplexer expansion by tying outputs together ? noninverting 3?state outputs ? outputs source/sink 24 ma ? act257 has ttl compatible inputs ? these are pb?free devices 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 oe i 0c i 1c z c i 0d i 1d z d si 0a i 1a z a i 0b i 1b z b gnd figure 1. pinout: 16?lead packages conductors (top view) www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 1 16 marking diagrams xxx = ac or act a = assembly location wl or l = wafer lot y = year ww or w = work week g or = pb?free package 1 16 xxx257g awlyww xxx 257 alyw 1 16 (note: microdot may be in either location)
mc74ac257, mc74act257 www. onsemi.com 2 pin name pin function s common data select input oe 3?state output enable input i 0a ?i 0d data inputs from source 0 i 1a ?i 1d data inputs from source 1 z a ?z d 3?state multiplexer outputs truth table output enable select input data inputs outputs oe s i 0 i 1 z h x x x z l h x ll l h x hh l l l xl l l h x h h = high voltage level l = low voltage level x = immaterial z = high impedance figure 2. logic symbol s oe i 0a i 1a i 0b i 1b z b i 0c i 1c i 0d i 1d z a z c z d functional description the mc74ac257/74act257 is a quad 2?input multiplexer with 3?state outputs. it selects four bits of data from two sources under control of a common data select input. when the select input is low, the i 0x inputs are selected and when select is high, the i 1x inputs are selected. the data on the selected inputs appears at the outputs in true (noninverted) form. the device is the logic implementation of a 4?pole, 2?position switch where the position of the switch is determined by the logic levels supplied to the select input. the logic equations for the outputs are shown below: z a = oe ? (i 1a ? s+i 0a ? s ) z b = oe ? (i 1b ? s+i 0b ? s ) z c = oe ? (i 1c ? s+i 0c ? s ) z d = oe ? (i 1d ? s+i 0d ? s ) when the output enable input (oe ) is high, the outputs are forced to a high impedance state. if the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. designers should ensure the output enable signals to 3?state devices whose outputs are tied together are designed so there is no overlap. note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. oe i 0a i 1a i 0b i 1b i 0c i 1c i 0d i 1d s z a z b z c z d figure 3. logic diagram
mc74ac257, mc74act257 www. onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage ?0.5 to +7.0 v v i dc input voltage 0.5 v cc +0.5 v v o dc output voltage (note 1) 0.5 v cc +0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias +150 c ja thermal resistance (note 2) soic tssop 69.1 103.8 c/w p d power dissipation in still air at 65 c (note 3) soic tssop 500 500 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 4) machine model (note 5) charged device model (note 6) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 7) 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed. 2. the package thermal impedance is calculated in accordance with jesd51?7. 3. 500 mw at 65 c; derate to 300 mw by 10 mw/ from 65 c to 85 c. 4. tested to eia/jesd22?a114?a. 5. tested to eia/jesd22?a115?a. 6. tested to jesd22?c101?a. 7. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v act 4.5 5.0 5.5 v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 3.0 v ? 150 ? v cc @ 4.5 v ? 40 ? ns/v v cc @ 5.5 v ? 25 ? t r , t f input rise and fall time (note 2) act devices except schmitt inputs v cc @ 4.5 v ? 10 ? ns/v v cc @ 5.5 v ? 8.0 ? t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. 1. 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac257, mc74act257 www. onsemi.com 4 dc characteristics symbol parameter v cc (v) 74ac 74ac unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 3.0 1.5 2.1 2.1 v out = 0.1 v 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 1.5 0.9 0.9 v out = 0.1 v 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 2.99 2.9 2.9 i out = ?50 a 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v *v in = v il or v ih 3.0 ? 2.56 2.46 ?12 ma 4.5 ? 3.86 3.76 i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 3.0 0.002 0.1 0.1 i out = 50 a 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v *v in = v il or v ih 3.0 ? 0.36 0.44 12 ma 4.5 ? 0.36 0.44 i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i oz maximum 3?state current v i (oe) = v il , v ih 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac257, mc74act257 www. onsemi.com 5 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74ac 74ac unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max t plh propagation delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3?5 i n to z n 5.0 1.5 4.0 6.0 1.0 7.0 t phl propagation delay 3.3 1.5 6.0 8.5 1.0 9.0 ns 3?5 i n to z n 5.0 1.5 4.5 6.0 1.0 7.0 t plh propagation delay 3.3 1.5 7.0 10.5 1.5 11.5 ns 3?6 s to z n 5.0 1.5 5.0 7.5 1.0 8.5 t phl propagation delay 3.3 1.5 7.5 10.5 1.5 11.5 ns 3?6 s to z n 5.0 1.5 5.5 7.5 1.0 8.5 t pzh output enable time 3.3 1.5 6.5 9.5 1.0 10.5 ns 3?7 5.0 1.5 5.0 7.5 1.0 8.5 t pzl output enable time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3?8 5.0 1.5 5.0 8.5 1.0 9.5 t phz output disable time 3.3 1.5 5.5 10.0 1.0 11.0 ns 3?7 5.0 1.5 5.0 9.0 1.0 10.0 t plz output disable time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3?8 5.0 1.5 5.0 8.0 1.0 9.0 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac257, mc74act257 www. onsemi.com 6 dc characteristics symbol parameter v cc (v) 74act 74act unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 4.5 1.5 2.0 2.0 v v out = 0.1 v 5.5 1.5 2.0 2.0 or v cc ? 0.1 v v il maximum low level input voltage 4.5 1.5 0.8 0.8 v v out = 0.1 v 5.5 1.5 0.8 0.8 or v cc ? 0.1 v v oh minimum high level output voltage 4.5 4.49 4.4 4.4 v i out = ?50 a 5.5 5.49 5.4 5.4 *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum 3?state current v i (oe) = v il , v ih 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time.
mc74ac257, mc74act257 www. onsemi.com 7 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74act 74act unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max t plh propagation delay i n to z n 5.0 1.5 5.0 7.0 1.0 7.5 ns 3?6 t phl propagation delay i n to z n 5.0 2.0 6.0 7.5 1.5 8.5 ns 3?6 t plh propagation delay s to z n 5.0 2.0 7.0 9.5 1.5 10.5 ns 3?6 t phl propagation delay s to z n 5.0 2.5 7.0 10.5 2.0 11.5 ns 3?6 t pzh output enable time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3?7 t pzl output enable time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3?8 t phz output disable time 5.0 2.5 6.5 9.0 1.5 10.0 ns 3?7 t plz output disable time 5.0 2.0 6.0 7.5 1.5 8.5 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v ordering information device order number package shipping ? mc74ac257dg soic?16 (pb?free) 48 units / rail mc74ac257dr2g soic?16 (pb?free) 2500 / tape & reel mc74ac257dtr2g tssop?16 (pb?free) 2500 / tape & reel MC74ACT257DG soic?16 (pb?free) 48 units / rail mc74act257dr2g soic?16 (pb?free) 2500 / tape & reel mc74act257dtr2g tssop?16 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc74ac257, mc74act257 www. onsemi.com 8 package dimensions tssop?16 dt suffix case 948f issue b *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* ??? ??? 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch
mc74ac257, mc74act257 www. onsemi.com 9 package dimensions soic?16 d suffix case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch 16 89 8x p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74ac257/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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